High-speed Interconnects in Modern VLSI Systems

Azita Emami, Assistant Professor of Electrical Engineering, Caltech

The implementation of high-performance computing systems strongly relies on the feasibility of high-bandwidth data communication between integrated circuit components (IC's). Moreover, future multi-core processors will need fast and robust intra-chip data transfer between the cores and memory units. Current trends of digital systems indicate that the amount of processing of each component or unit is expected to continue to increase exponentially at least for the next 10 years. In order to scale the communication bandwidth with the same trend, both the number of IO's and the data-rate per IO link need to increase. A number of limitations such as the bandwidth of the wires, area and power consumption per IO, interferences, and characteristics of the highly scaled devices make the design of high-speed IO's very difficult.

This talk will focus on low-power system and circuit solutions for parallel chip-to-chip interconnections and intra-chip networks. As the data-rates over the conventional wires increase, the complexity of required equalization and coding schemes increase rapidly. The design challenges of wireline data communication and the possibility of using optics for interconnection at short distances will be discussed. We will focus on a number of novel low-power solutions for both electrical and optical signaling, and the scaling properties these solutions for the future systems.

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