CS137a

Definitions and explanations for unfamiliar terms

• Day 1: January 5, 2004
  • RTL: Register-Transfer-Level -- design level where the user describes the logic which occurs between clock edges (i.e. the logic as data is transfered from one set of registers to the next). Both Verilog and VHDL (VHSIC [Very High Speed Integrated Circuit] Hardware Description Language) can both be used for RTL design (they can also be used for behavioral design).
• Day 2: January 7, 2004
  • DAG: Directed Acylic Graph -- A directed graph with no cycles. DAGs exist when there is fanout; that is, the output of a logic gate is used by more than one succeeding gate.