Caltech Seal Computing Beyond Silicon Summer School
 

Projects (Not final...many questions still to add)

 

There is now a page for the Project timeline.

Here are some suggested project starting points. The description is intended to give you enough of a flavor of a project to get you started. What the project actually is will be up to you; the listed contact (and likely other participating faculty) will be happy to discuss the project and attacks in more detail. We're expecting groups of 4--5 students to work together on each project.

These are intended to be starter research projects. We don't know what the answers are (but probably have wild ideas about where one might start looking). We think that a small group of students can come up with an interesting start on the problem, at least, in 3--4 weeks.


  • The costs of given process technology improvements must be weighed against their respective benefits. Consider a set of improvements spanning material (copper vs. aluminum, and low-k inter-layer dielectric vs. SiO2), lithography (reduction of poly half-pitch vs. reduction of contacted M1 half-pitch), and integration (stacking of two bumped die, vs. single-die integration). Making (and documenting!) whatever assumptions you find necessary (e.g., a wirelength distribution model, an architecture model, etc.) determine which of the above improvements will result in the greatest performance gains for future versions of the ITRS ``high-performance MPU''. [contact: Kahng]
  • Estimate logic density in a nanoscale (molecular) PLA array for some of the following:
    • 4b-ALU (e.g. consider LS181), n-bit ALU using multiple arrays?
    • MCNC FSM benchmarks (trivial mapping)
    • MCNC benchmarks ... with some decomposition/routing strategy
    • ALU with fault detection
    • ECC unit
    What does this suggest about the detail design of nanoscale PLA blocks? [contact: DeHon]
  • Develop a scheme and architecture for expanding, self-diagnostic and configuration of a molecular PLA/memory system [contact: DeHon]
  • Develop a (non-rollback) online fault-tolerant universal logic scheme. [contact: DeHon]
  • Sketch plausible scheme for electrical 3D, nanoscale logic/memory architecture:
    • assembly techniques
    • interconnect design
    • energy/heat management
    • usage strategy
    [contact: DeHon]
  • Develop alternate schemes for nanoscale array manufacture which avoid nanoscale precision stamps. (e.g. developing ideas to exploit modulation doping is one promising direction, but maybe you can suggest others.) Consider how might allow construction of address decoder and other fixed patterns (e.g. fixed OR plane in PAL). [contact: DeHon]
  • How common is Turing-universal behavior?  I.e., given a (SM,TM,CA,BCA,etc) chosen "at random", what is the probability that the chosen machine is a universal computer?  This may be uncomputable (can you prove it?), or perhaps a lower or upper bound can be shown. [contact: Winfree]
  • Consider the following error-prone modification of the Tile Assembly Model: at each step, with probability p a tile is added in accord with T=2, and with probability 1-p a tile is added in accord with T=1.  Can reliable computation be performed in this model?  I.e., given a set of tiles that compute correctly when p=0 but (probably) incorrectly if p>0, find a set of tiles which compute with a higher probability of success in the error-prone model.  (You might try a 3D version of the Tile Assembly Model, and/or T=3.) [contact: Winfree]
  • Can interesting circuits be algorithmically self-assembled?  Construct tile sets ("painted" with circuit elements) that self-assemble into common circuits, such as adders, multipliers, buffers, sorters, etc. [contact: Winfree]
  • Does Bennett's hypothetical enzymatic Turing Machine really work?  Develop a simulation, and analyze the speed-energy trade-off. Propose how to build a biochemical Turing Machine using known enzymes. [contact: Winfree]
  • Suppose we have many bacterial cells, at various fixed locations in the plane, subject to an external chemical gradient that varies from low to high concentrations.  Design a genetic regulatory network that performs an analog-to-digital computation, turning on gene n iff nth bit of the binary number representing the concentration is 1.  Compare this to the formation of stripes in Drosophila embryos. [contact: Winfree]
  • Design a kinase cascade system (reactions of the form A + B <--> A + B*, etc) that transmits signals (A vs A*, B vs B*, etc) reliably along a long chain, even in the limit of a small number of molecules.  Consider using handshaking protocols. [contact: Winfree
  • What is the smallest kinase cascade system  that can multiply two binary numbers?  Consider both a "fully digital" circuit design, and a design based on digital-to-analog and analog-to-digital stages with analog computation in the middle.  Which design is smaller, and which is more reliable in the limit of a small number of molecules? [contact: Winfree]


CBSSS Syllabus
CBSSS